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| DATA SHEET MOS INTEGRATED CIRCUIT PD6708 IEBusTM (Inter Equipment BusTM) PROTOCOL CONTROL LSI DESCRIPTION The PD6708 is a peripheral LSI for microcontrollers that controls the protocol of the IEBus. This LSI processes the protocol of the IEBus. Because it is provided with a transmit/receive buffer, the microcontroller can concentrate on the application processing of the IEBus. Because the PD6708 also contains an IEBus driver/receiver, it can be directly connected to the bus. FEATURES * Protocol control of IEBus * Multi-master system * Broadcast communication function (communication between one unit and multiple units) * Choice of three modes with different transmission speeds At 12 MHz Mode 0 Mode 1 Mode 2 Approx. 3.9 Kbps Approx. 17 Kbps Approx. 26 Kbps At 12.58 MHz Approx. 4.1 Kbps Approx. 18 Kbps Approx. 27 Kbps * On-chip IEBus driver/receiver * Transmit/receive buffer Transmit: 4-byte FIFO Receive: 20-byte FIFO * Interface with microcontroller * Three-line serial I/O (SCK, SO, SI pins) * Transfer with MSB first * Oscillation frequency (fX): 12 MHz, 12.58 MHz * In modes 0 and 1: 1.5 % * In mode 2: 0.5 % * Supply voltage: VDD = 5 V 10 % ORDERING INFORMATION Part Number Package 16-pin plastic DIP (300 mil) 16-pin plastic SOP (300 mil) PD6708CX PD6708GS APPLICATION FIELD Fields where a small-scale digital data transfer system is required between equipment, such as automobile electronic systems and industrial equipment The information in this document is subject to change without notice. The mark 5 shows major revised points. Document No. U10680EJ2V0DS00 (2nd edition) (Previous No. IC-3282) Date Published January 1996 P Printed in Japan (c) 1993 PD6708 PIN CONFIGURATION (TOP VIEW) * 16 pin plastic DIP (300 mil) PD6708CX * 16 pin plastic SOP (300 mil) PD6708GS SCK 1 16 VDD SI 2 15 TEST SO 3 14 RESET IRQ 4 13 CS R/W 5 12 C/D XI 6 11 AVDD XO 7 10 BUS+ GND 8 9 BUS- SCK SI SO IRQ R/W XI, XO GND BUS-, BUS+ AVDD C/D CS RESET TEST VDD : Serial clock input : Serial data input : Serial data output : Interrupt request output : Read/write switchover input : System clock : Ground : IEBus input/output : IEBus analog power supply (connected to VDD pin) : Command/data switchover input : Chip select input : Reset input : Test input (connected to VDD pin) : Positive power supply 2 PD6708 CONTENTS 1. 2. PIN FUNCTIONS ......................................................................................................................................... 5 1.1 List of Pin Functions ......................................................................................................................................... 5 IEBus OPERATION .................................................................................................................................... 6 2.1 2.2 Operation Overview ........................................................................................................................................... 6 IEBus Communication Protocol ...................................................................................................................... 7 2.2.1 Bus mastership determination (arbitration) ................................................................................... 8 2.2.2 Communication modes ...................................................................................................................... 8 2.2.3 Communication address ................................................................................................................... 9 2.2.4 Broadcast communication ................................................................................................................ 9 Transfer Protocol ............................................................................................................................................. 10 Transfer Data (Contents of Data Field) ......................................................................................................... 16 Bit Format ......................................................................................................................................................... 19 2.3 2.4 2.5 3. INTERNAL CONFIGURATION ................................................................................................................. 20 3.1 3.2 3.3 3.4 Data Link Layer Controller ............................................................................................................................. 21 Physical Layer Controller ............................................................................................................................... 21 IEBus Driver/Receiver ..................................................................................................................................... 21 Host Interface ................................................................................................................................................... 21 4. INTERFACING WITH HOST CONTROLLER .......................................................................................... 22 4.1 Accessible Buffers and Registers from Host Controller ........................................................................... 22 4.1.1 Write data buffer (WDB) .................................................................................................................. 22 4.1.2 Read data buffer (RDB) ................................................................................................................... 22 4.1.3 Command register (CMR) ................................................................................................................ 22 4.1.4 Status register (STR) ....................................................................................................................... 23 Host Interface Modes ...................................................................................................................................... 23 4.2.1 Switching through pin control ....................................................................................................... 24 4.2.2 Switching through software control .............................................................................................. 26 Reset Mode ....................................................................................................................................................... 28 4.2 4.3 5. COMMUNICATION CONTROL COMMANDS ......................................................................................... 30 5.1 5.2 Overview of Communication Control Commands....................................................................................... 30 Communication Control Command Functions ............................................................................................ 31 5.2.1 INIT command (command code: 0000).......................................................................................... 31 5.2.2 SETSA command (command code: 0001) .................................................................................... 32 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 MREQ1 command (command code: 0010) ................................................................................... 33 MREQ2 command (command code: 0011) ................................................................................... 34 ABORT command (command code: 0100) ................................................................................... 34 SETSD command (command code: 0101) .................................................................................... 35 GETSTA command (command code: 0110) .................................................................................. 36 SETREV command (command code: 0111) .................................................................................. 37 6. RETURN CODES ...................................................................................................................................... 38 6.1 6.2 6.3 6.4 6.5 Return Return Return Return Return Codes Codes Codes Codes Codes in Master/Slave Data Transmission ..................................................................................... 38 in Master Reception ............................................................................................................... 38 in Slave Reception ................................................................................................................. 39 in Broadcast Reception ......................................................................................................... 39 Generation Intervals ............................................................................................................... 40 7. COMMUNICATING WITH HOST CONTROLLER ................................................................................... 43 7.1 Master Transmission ....................................................................................................................................... 43 7.1.1 Master transmission by MREQ1 command .................................................................................. 43 7.1.2 Master transmission by MREQ2 command .................................................................................. 44 3 PD6708 7.2 7.3 7.4 7.5 Slave Transmission ......................................................................................................................................... 44 7.2.1 Data transmission ............................................................................................................................ 44 7.2.2 Transmitting slave status address and lock address ................................................................. 45 Master Reception ............................................................................................................................................. 45 Slave Reception ............................................................................................................................................... 46 Broadcast Reception ....................................................................................................................................... 47 8. EXAMPLE OF HOST CONTROLLER PROCESSING FLOW ................................................................ 48 8.1 8.2 8.3 Main Routine ..................................................................................................................................................... 48 Interrupt Service Routine ................................................................................................................................ 49 Processing Routine ......................................................................................................................................... 50 8.3.1 PD6708 initialization routine ......................................................................................................... 50 8.3.2 Communication control command processing routine .............................................................. 51 8.3.3 8.3.4 8.3.5 Master transmission processing routine ...................................................................................... 57 Slave data transmission processing routine ............................................................................... 58 Master reception processing routine ............................................................................................ 59 9. ELECTRICAL SPECIFICATIONS ............................................................................................................ 63 10. PACKAGE DRAWINGS ............................................................................................................................ 67 11. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 69 APPENDIX MAJOR DIFFERENCES BETWEEN PD6708 AND PD72042A, PD72042B ................... 70 4 PD6708 1. PIN FUNCTIONS 1.1 List of Pin Functions Pin No. 1 2 3 4 Pin Name SCK SI SO IRQ Input/Output Input Input Output Output Function Input for serial clock used to interface with microcontroller. Input for serial data used to interface with microcontroller. Output for serial data used to interface with microcontroller. Output used by interrupt request signals generated by communication and command execution results. Used as operation start request signal to microcontroller. The interrupt request signal is output for 8 s or longer at high level. I/O Format CMOS input CMOS input CMOS output CMOS output At Reset Input Input High level Low level 5 R/W Input Input for switching serial interface read/write mode. When high, it is in the read mode. When low, it is in the write mode. When this pin is low and C/D pin high, the read and write modes can be switched by commands input from the serial interface. Connection pins for system clock resonator. Use a 12- or 12.58-MHz crystal, or ceramic resonator. Frequency precision depends on the communication mode used. Mode 0 : 1.5 % Mode 1 : 1.5 % Mode 2 : 0.5 % Ground Input/output for IEBus. CMOS input Input 6 7 XI XO -- -- (Oscillation continues) 8 9 10 11 12 GND BUS- BUS+ AVDD C/D -- Input/output -- -- -- High impedance -- Input -- Input IEBus driver/receiver analog power supply. Connect to VDD. Input used to switch between processing data input to the serial interface as commands or data. When set to high, data is processed as commands; when low, data is processed as data. When this pin is high and R/W pin low, the read and write modes can be switched by commands input from the serial interface. Chip select input. When low, serial interface input is enabled. When high, serial clock (SCK) input is disabled, SO pin becomes high impedance, and the serial clock counter is reset. The status of CS pin is not affected by IEBus transmit and receive operations. System reset signal input pin. Low input effects a reset. Always input the low signal for 6 s or longer after turning on the power. Always connect this pin to the VDD. Positive power supply input. Apply a voltage of 5 V 10 %. -- CMOS input 13 CS Input CMOS input Input 14 RESET Input CMOS input Input 15 16 TEST VDD Input -- CMOS input -- -- -- 5 PD6708 2. IEBus OPERATION 2.1 Operation Overview The PD6708 is an IEBus interface CMOS LSI device. The IEBus is a bus for a small-scale digital data transfer system designed to transfer data between electronic devices. The PD6708 is connected to a microcontroller incorporated in electronic equipment with a serial interface (SCK, SO, SI pins). The data and commands required to transfer data with the host controller (microcontroller) are set via this serial interface. When the host controller transmits data to the PD6708 via the serial interface, signals are output from the BUS pins (BUS+ and BUS-). Data received from the BUS pins can be read by the host controller via the serial interface. 5 6 PD6708 2.2 IEBus Communication Protocol An overview of the IEBus is as follows. * * Communication system: Half-duplex asynchronous communication Multi-master system All the units connected to the IEBus can transfer data to the other units. * Broadcast communication function (communication between one unit and multiple units) Group broadcast communication: Broadcast communication with group units General broadcast communication: Broadcast communication with all units. * Three modes with different transfer speeds selectable. fX = 12 MHz fX = 12.58 MHz Maximum Number of Transfer Bytes (bytes/frame) 16 32 128 5 Mode 0 Mode 1 Mode 2 Approx. 3.9 Kbps Approx. 17 Kbps Approx. 26 Kbps Approx. 4.1 Kbps Approx. 18 Kbps Approx. 27 Kbps * Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) The priority order for bus occupancy is as follows. <1> Broadcast communication takes precedence over ordinary communication (i. e., communication between one unit and another). <2> The lowest master address has the highest priority. * Communication scale Number of units: Cable length: Load capacity: MAX. 50 MAX. 150 m (with twisted-pair cable Terminating resistor: 120 7 PD6708 2.2.1 Bus mastership determination (arbitration) When a unit connected to the IEBus controls another unit, it performs an operation to occupy the bus. This operation 5 is called arbitration. Arbitration is to select one unit, and if several units begin to transmit data simultaneously, gives permission to occupy the bus to that one unit. So that one unit is granted the permission to occupy the bus as a result of the arbitration, the following priority conditions are determined. Remark The units not given permission through arbitration are automatically allowed to get into retransfer mode (number of retransfer times for the PD6708: 3). (1) Priority according to type of communication Broadcast communication (between a single and multiple units) takes precedence over ordinary communication (between single units). (2) Priority according to master address If the communication devices are of the same type, the unit with the lowest master address has the highest priority. Example The master address comprises 12 bits, and unit 000H has the highest priority while unit FFFH has the lowest priority. 2.2.2 Communication modes The IEBus is provided with three communication modes with different transfer speeds. The transfer speed and maximum number of transfer bytes in a single communication frame in each communication mode are shown in Table 2-1. Table 2-1. Transfer Speed and Maximum Number of Transfer Bytes in Each Communication Mode Communication Mode Maximum Number of Transfer Bytes (bytes/frame) Actual Transfer Speed fX = 12 MHz 0 1 2 16 32 128 Note 2 Note 1 (Kbps) Note 2 fX = 12.58 MHz Approx. 4.1 Approx. 18 Approx. 27 Approx. 3.9 Approx. 17 Approx. 26 Notes 1. Actual transfer speed when the maximum number of bytes is transferred 2. Oscillation frequency when the PD6708 is used Cautions 1. A communication mode is selected for each unit connected to the IEBus before communication is performed. If the communication mode of the master unit is not the same as that of the unit with which the master unit is to communicate (slave unit), communication cannot be performed correctly. 2. If the oscillation frequency of one unit is fx = 12 MHz and that of the other unit is fx = 12.58 MHz, communication cannot be performed correctly even if the communication mode is the same. Make sure that the oscillation frequencies of the two units to communicate are the same. 8 PD6708 2.2.3 Communication address With the IEBus, a 12-bit communication address is assigned to each unit. The communication address is made up as follows. Higher 4 bits: Group number (number which identifies the group to which the unit belongs) Lower 4 bits: Unit number (number which identifies a unit within a group) 2.2.4 Broadcast communication In ordinary communication, there is only one master unit and one slave unit, and transmission or reception is performed on an one-to-one basis. In broadcast communication, however, there are a number of slave units and the master unit performs transmission with these slave units. Because there are several slave units, no acknowledge signals is returned from the slave units during communication. Whether broadcast communication or ordinary communication is performed is specified by the broadcast bit (for the broadcast bit, see 2.3 (1) <2> "Broadcast bit"). There are two kinds of broadcast communication, as follows. (1) Group broadcast communication Broadcast communication is performed to the units in a group whose group numbers are the same as that specified by the higher 4 bits of the communication address. (2) General broadcast communication Broadcast communication is performed to all units irrespective of their group numbers. Group broadcast communication or general broadcast communication is identified by the value of a salve address (for the slave address, see 2.3 (3) "Slave address field"). 5 9 PD6708 2.3 Transfer Protocol The IEBus transfer signal format is shown in Figure 2-1. Data is transferred as a series of signals called a communication frame. The number of data that can be transferred in one communication frame and the transfer speed differ depending on the communication mode. Figure 2-1. Transfer Signal Format (fx = at 12 MHz) 5 Field Name Number of Bits Header 1 1 Master Address Field 12 1 Slave Address Field 12 11 Control Field 4 1 1 Message Length Field 8 11 A Data Field 8 Data Bit 1 P 1 A 8 Data Bit 1 P 1 A BroadStart cast Master P Slave P Address Bit Bit Address Transfer Time Mode 0 Mode 1 Mode 2 A Control P Bit Message A Length P Bit Approx. 7330 s Approx. 2090 s Approx. 1590 s Approx. 1590 x N s Approx. 410 x N s Approx. 300 x N s P: Parity bit (1 bit) A: Acknowledge bit (1 bit) When A = 0: ACK When A = 1: NAK N: Number of data bytes Remark In broadcast communication, the value of the acknowledge bit is ignored. (1) Header A header comprises a start bit and a broadcast bit, as described below. <1> Start bit The start bit is a signal which tells the other units that data transmission will start. The unit which is about to start transmitting data will output the low signal (the start bit) for a specified time, and then outputs the broadcast bit. If another unit is already outputting a start bit before one unit outputs a start bit, the unit will not output the start bit. It will wait until the another unit completely outputs the start bit, and then outputs the broadcast bit. The units other than the one that has started transmission detect this start bit and enters the reception state. <2> Broadcast bit The broadcast bit distinguishes between broadcast communication and ordinary communication. When this bit is `0', it indicates broadcast communication; when it is `1', it indicates ordinary communication. There are two types of broadcast communication: group broadcast and general broadcast. These types are identified by the value of the slave address (for the slave address, see (3) "Slave address field"). In broadcast communication, there are a number of slave units. Therefore, the acknowledge bit is not returned in the fields described in (2) below and onward. If two or more units start to transmit a communication frame simultaneously, broadcast communication takes precedence over ordinary communication, and wins in the arbitration. 10 PD6708 (2) Master address field The master address field is used to transmit the unit address of the master unit (master address) to the other units. The master address field consists of master address bits and a parity bit. The master address comprises 12 bits and is output from the MSB. If two or more units start transmitting the broadcast bit of the same value simultaneously, the arbitration decision is made by the master address field. The master address field compares the data the master has output with the data on the bus each time the master transmits 1 bit of data. If the master address output by the master unit is different from the data on the bus, the master unit assumes that it has lost in arbitration, stops transmission, and enters the reception state. Because the IEBus has a wired-AND configuration, the unit having the lowest master address of the units participating in the arbitration (arbitration masters) wins in the arbitration. Ultimately, only one unit remains in the transmission state as the master unit after outputting a 12-bit master address. This master unit then outputs a parity bit slave address field. Note Note 5 , makes the other units confirm the master address, and then outputs the Even parity is used. When the number of the bits that are `1' in the master address is odd, the parity bit is `1'. (3) Slave address field The slave address field is used to transmit the address (slave address) of a unit (slave unit) with which the master wishes to communicate. The slave address field consists of slave address bits, a parity bit, and an acknowledge bit. The slave address comprises 12 bits and is output from the MSB. After the 12-bit slave address is transmitted, the parity bit is output to prevent the slave address from being received incorrectly. Next, the master unit looks for the acknowledge signal (bit) from the slave unit to confirm that the slave unit exists on the bus. When the master unit detects the acknowledge signal, it starts outputting the control field. In the case of broadcast communication, however, the master unit outputs the control field without waiting for the acknowledge bit. A slave unit outputs the acknowledge signal if it has detected that its slave address coincides with that selected by the master and that the parities of both the master and slave addresses are even. If the parity is odd, the slave unit assumes that the master or slave address has not been correctly received, and does not output the acknowledge signal. In this case, the master unit enters the standby (monitor) state and communication ceases. In the case of broadcast communication, the slave address is used to distinguish between group broadcast and general broadcast as follows: Slave address = FFFH: General broadcast communication Slave address FFFH: Group broadcast communication Remark In the case of group broadcast communication, the group number is the value of higher 4 bits of the slave address. 11 PD6708 5 (4) Control field The control field indicates the type of data and the transfer direction of the subsequent data field. The control field consists of 4 control bits, a parity bit, and an acknowledge bit. The control bits are output from the MSB. A parity bit is output after the control bits. When the parity is even and the slave can execute the function requested by the master unit, the slave unit outputs an acknowledge signal, and then outputs the next message length field. If the slave unit cannot execute the function requested by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal but returns to the standby (monitor) state. After the master unit has confirmed the acknowledge signal, it starts outputting the next message length field. If the master unit is cannot confirm the acknowledge signal, it enters the standby state and stops communication. In the case of broadcast communication, however, the master unit starts outputting the message length field without confirming the acknowledge signal. For the functions of the control bits, see Table 2-3. (5) Message length field The message length field is used to specify the number of communication data bytes. The message length field comprises 8 message length bits, a parity bit and, an acknowledge bit. The message length bits are output from the MSB. The message length bits indicate the number of communication data bytes as shown in Table 2-2. Table 2-2. Meaning of Message Length Bits Message Length Bits (hex) 01H 02H : : FFH 00H Number of Transmission Data Bytes 1 byte 2 bytes : : 255 bytes 256 bytes Remark In the communication mode, if the number of bytes exceeding the maximum number of transfer bytes per frame is set, two or more frames are communicated. In this case, the message length bits indicate the number of remaining communication data bytes during the second communication and onward. The operation of this field differs depending on whether the master transmits (bit 3 of control bits is 1) or receives (bit 3 of control bits is 0) data. <1> When master transmits data The message length bits and parity bit are output by the master unit. The slave unit outputs the acknowledge signal and then the next data field if it detects that the parity is even. The slave unit does not output the acknowledge signal in the case of broadcast communication. If the parity is odd, the slave unit assumes that the message length bits have not been received correctly, and returns to the standby (monitor) state without outputting the acknowledge signal. In this case, the master unit also returns to the standby state, and communication ceases. 12 PD6708 <2> When master receives data The message length bits and parity bit are output by the slave unit. The master unit outputs the acknowledge signal if it detects that the parity bit is even. If the parity is odd, the master unit assumes that the message length bits have not been received correctly, and returns to the standby state without outputting the acknowledge signal. In this case, the slave unit also returns to the standby state, and communication ceases. (6) Data field The data field is used to transmit/receive data to/from the slave units. The master unit uses the data field to transmit data to and receive data from the slave units. The data field consists of 8 data bits, a parity bit, and an acknowledge bit. The data bits are output from the MSB. Following the data bits, the parity bit and acknowledge bit are output from the master unit and the slave unit, respectively. Broadcast communication is performed when only the master unit transmits data. At this time, the acknowledge signal is ignored. The operation differs depending on whether the master performs transmission or reception, as follows. <1> When master transmits data When the master unit writes data to the slave unit, the master unit transmits data bits and a parity bit to the slave unit. The slave unit receives the data bits and parity bit. If the parity is even and the receive buffer is empty, the slave unit outputs the acknowledge signal. If the parity is odd and the receive buffer is not empty, the slave unit denies acknowledgment of the corresponding data and does not output the acknowledge signal. If no acknowledge signal is output from the slave unit, the master unit transmits the same data again. The master unit continues this operation until it detects the acknowledge signal from the slave unit or the data reaches the maximum number of transfer bytes. If the parity is even and the acknowledge signal has been output from the slave unit, and if the master unit has more data to transmit and the maximum number of transfer bytes is not exceeded, the master unit will transmit the next data. In the case of broadcast communication, the slave unit does not output the acknowledge signal, and the master unit transfers data on a byte-by-byte basis. <2> When master receives data When the master unit reads data from the slave unit, the master unit outputs synchronization signals corresponding to all the read bits. The slave unit outputs the contents of the data and parity bits onto the bus in accordance with the synchronization signals from the master unit. The master unit reads the data and parity bit output by the slave unit, and checks the parity. If the parity is odd or the receive buffer is not empty, the master unit denies acknowledgement of that data and does not output the acknowledge signal. If the data is within the maximum number of transfer bytes that can be transmitted in one frame, the master unit repeatedly reads the same data. If the parity is even and the receive buffer is empty, the master unit acknowledges the data and transmits back the acknowledge signal. If the data is within the maximum number of bytes that can be transmitted in one frame, the master unit reads the next data. 5 5 13 PD6708 (7) Parity bits Parity bits are used to check that there is no error in the transfer data. A parity bit is added to the master address bits, slave address bits, control bits, message length bits, and data bits. Even parity is used. If the number of the bits that are `1' bits in data is odd, the parity bit is `1', and if the number of the bits that are `1' bits is even, the parity bit is `0'. (8) Acknowledge bits In ordinary communication (between two units), an acknowledge bit is added to the following places to confirm that data has been acknowledged correctly. * * * * At the end of the slave address field. At the end of the control field. At the end of the message length field. At the end of a data field. The definition of the acknowledge bit is as follows. * * `0': Indicates that transfer data has been acknowledged (ACK). `1': Indicates that transfer data has not been acknowledged (NAK). Note that the value of the acknowledge bit is ignored in broadcast communication. <1> Acknowledge bit at the end of the slave field When any of the following conditions is met, the acknowledge bit at the end of the slave field is NAK, and communication is discontinued. * * * If the parity of the master address bits or slave address bits is incorrect. If a timing error (error in bit format) occurs. If the slave unit does not exist. <2> Acknowledge bit at the end of the control field When any of the following conditions is met, the acknowledge bit at the end of the control field is NAK, and communication is discontinued. * * * * * * * Note If the parity of the control bits is incorrect. If bit 3 of the control bits is `1' (write operation) when the slave receive buffer 5 Note is not empty. If the control bits indicate read operation (3H or 7H) when the slave transmit buffer Note is empty. If 3H, 6H, 7H, AH, BH, EH, or FH of control bits is requested from a unit other than the unit which set the lock when a lock has been set. If the control bits indicate lock address read (4H) when a lock has not been set. If a timing error occurs. If the control bits are undefined. See 2.4 (1) "Reading slave status (SSR) (control bit: 0H, 6H)". 14 PD6708 <3> Acknowledge bit at the end of a message length field When either of the following conditions is met, the acknowledge bit at the end of the message length field is NAK, and communication is discontinued. * * If the parity of the message length bits is incorrect. If a timing error occurs. <4> Acknowledge bit at the end of a data field When any of the following conditions is met, the acknowledge bit at the end of a data field is NAK, and communication is discontinued. * * * Note If the parity of the data bits is incorrect Note . If a timing error occurred in or after the previous acknowledge bit transmission. If the receive buffer is full and cannot accept any more data Note. In this case, if the number of transfer bytes is within the maximum number of bytes which can be transmitted, the transmitting side re-executes transmission of that data field. 15 PD6708 2.4 Transfer Data (Contents of Data Field) The contents of the data field are data specified by the control bits. Table 2-3. Functions of Control Bits 5 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Bit 3 Note 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reads slave status (SSR) Undefined Undefined Reads and locks data Function Note 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Reads lock address (lower 8 bits) Reads lock address (higher 4 bits) Reads and unlocks slave status (SSR) Reads data Undefined Undefined Writes and locks command Writes and locks data Undefined Undefined Writes command Writes data Notes 1. Depending on the value of bit 3 (MSB), the transfer direction of the message length bits of the subsequent message field and data field differs. When bit 3 is "1", data are transferred from the master unit to the slave unit. When bit 3 is "1", data are transferred from the slave unit to the master unit. 2. 3H, 6H, AH, and BH are control bits that specify locking or unlocking. If any of undefined values 1H, 2H, 8H, 9H, CH, or DH is transmitted, no acknowledge bit is returned. A unit locked by the master unit rejects acknowledging the control bits and does not output the acknowledge bit if the control bits received from the master unit which requested locking is in any other state than that shown in Table 2-4. Table 2-4. Control Field Corresponding to Locked Slave Unit Bit 3 0H 4H 5H 0 0 0 Bit 2 0 1 1 Bit 1 0 0 0 Bit 0 0 0 1 Reads slave status Reads lock address (lower 8 bits) Reads lock address (higher 4 bits) Function 16 PD6708 (1) Reading slave status (SSR) (control bit: 0H, 6H) The master unit can learn the reason why the slave unit has not returned the acknowledge bit (ACK) by reading the slave status. The slave status is determined by the results of the last communication performed by the slave unit. All the slave units can provide slave status information. The meanings of the slave status are shown in Table 2-5. Figure 2-2. Bit Configuration of Slave Status (SSR) 5 MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 Table 2-5. Meanings of Slave Status Bit Bit 0 Note 1 Value 0 1 Slave transmit buffer empty Meaning Slave transmit buffer is not empty. Slave receive buffer empty Slave receive buffer is not empty. Unit is not locked. Unit is locked. Fixed to `0' Slave transmission ends Slave transmission enabled Fixed to `0' Mode 0 Mode 1 Mode 2 For future expansion Indicates the highest mode the unit supports Note 4 Bit 1 Note 2 0 1 Bit 2 0 1 Bit 3 Bit 4 Note 3 0 0 1 Bit 5 Bit 7 Bit 6 0 00 01 10 11 . Notes 1. The slave transmit buffer is the buffer accessed during data read processing (control bits: 3H, 7H). With the PD6708, this buffer corresponds to the write data buffer (WDB) when the SETSD command is valid (see 5.2.6 "SETSD command"). 2. The slave receive buffer is the buffer accessed during data write processing (control bits: 8H, AH, BH, EH, FH). With the PD6708, this buffer corresponds to the read data buffer (RDB). 3. The value of bit 4 can be selected by INIT command (see 5.2.1 "INIT command"). 4. Because the PD6708 can support mode 2, bits 7 and 6 are fixed at `10'. 17 PD6708 (2) Transferring data command (control bit: read (3H, 7H), write (AH, BH, EH, FH)) During data read (3H, 7H), the data in the data buffer of the slave unit are read to the master unit. During data write (BH, FH) or during command write (AH, EH), the data the slave unit has received are processed according to the operation convention. Remarks 1. 2. (3) 5 The user can voluntarily select data and command as his system requires. Control bits 3H, AH, and BH may be locked depending on the communication condition and status. Reading lock address (control bits: 4H, 5H) When the lock address is read processing (4H, 5H), the address (12 bits) of the master unit that has issued the lock instruction is read in 1-byte units, as shown below. Figure 2-3. Lock Address Configuration MSB Control Bits : 4H Lower 8 Bits LSB Control Bits : 5H Undefined Higher 4 Bits (4) Locking and unlocking (locking (3H, AH, BH), unlocking (6H)) The lock function is used to transfer a message over two or more frames. A locked unit receives data only from the unit that has locked the unit. Locking and unlocking are performed as described below. <1> Locking After the transmission/reception of the acknowledge bit `0' of the message length field by the control bits (3H, AH, BH) which specify the lock has ended, if the communication frame is completed without completing the transmission or reception of the number of data bytes specified by the message length bits, the slave unit is locked by the master unit. At this time, the bit (bit 2) relating to the locking of the byte which indicates the slave status is set to `1'. <2> Unlocking After completion of transmission or reception of data in one frame by the number of data bytes specified by the message length bits with control bits (3H, AH, or BH) specifying locking or control bits (6H) specifying unlocking, the slave unit is unlocked by the master unit. At this time, the bit (bit 2) relating to the locking of the byte which indicates the slave status is reset to `0'. Locking and unlocking are not performed in the case of broadcast communication. Caution To unlock the unit specified to be unlocked by the unit itself, the INIT command (see 5.2.1 "INIT command") must be executed with the PD6708 (Whether a unit is locked or not can be checked by using the GETSA command (see 5.2.7 "GETSA command"). 18 PD6708 2.5 Bit Format The IEBus communication frame bit format (concept) is shown in Figure 2-4. Figure 2-4. IEBus Bit Format (Concept) Logic "1" 5 Logic "0" Preparation Period Synchronous Period Data Period Preparation Period Synchronous Period Data Period Logic "1": Potential difference between bus lines (BUS+ pin and BUS- pin) is 20 mV or lower (low level). Logic "0": Potential difference between bus lines (BUS+ pin and BUS- pin) is 120 mV or higher (high level). Preparation period: The first or subsequent low-level (logic "1") period Synchronous period: The next high-level (logic "0") period Data period: The period that expresses the bit value (logic "1": low level; logic "0": high level) The synchronous period and data period have approximately the same length. The IEBus uses bit-by-bit synchronization. The specifications for the total bit time and the periods allocated to the bits depend on the type of transfer bit, and on whether the unit is the master unit or the slave unit. 19 PD6708 3. INTERNAL CONFIGURATION The PD6708 is composed of the following four blocks. (1) Data link layer controller (2) Physical layer controller (3) IEBus driver/receiver (4) Host interface Figure 3-1. PD6708 Internal Blocks Host Interface Status Register (STR) Data Link Layer Controller Read Data Buffer (RDB) 20 Bytes Shift Register Write Data Buffer (WDB) 4 Bytes BUS+ Receiver Filter BUS- Driver IEBus Driver/Receiver Physical Layer Controller Bit Sequencer Command Register (CMR) Serial I/O Controller CS IRQ C/D R/W SO SCK SI 20 PD6708 3.1 Data Link Layer Controller The data link layer controller performs processing of the IEBus protocol data link layer (frame composition and resolution, communication error detection, etc.), execution of communication control commands set by the host controller, and generate a return code that informs the host controller of the communication status. 3.2 Physical Layer Controller The physical controller performs generation and resolution of bit timing and also converts the signals between the bus lines through the driver/receiver. 3.3 IEBus Driver/Receiver The driver/receiver performs conversion between the logic signals within the PD6708 and the IEBus signals. The IEBus signals and their relationship to the logic statuses are shown in Table 3-1. Table 3-1. Relationship between IEBus Signals and Logical Statuses Logical Status 0 1 IEBus Signals (BUS+) - (BUS-) 120mV (BUS+) - (BUS-) 20mV 3.4 Host Interface The host Interface is a block which controls the transmission and reception of data to and from the host controller. It accepts communication control commands, passes on return codes, and forwards transmit data. The forwarding of transmit data takes place through the FIFO buffers, 4 bytes of write data buffer (WDB) and 20 bytes of read data buffer (RDB). It also absorbs the differences between IEBus transmission speed and the transmission speed on the serial interface between the PD6708 and the host controller. 21 PD6708 4. INTERFACING WITH HOST CONTROLLER This chapter will explain the interfacing that occurs between the PD6708 and the host controller. 4.1 Accessible Buffers and Registers from Host Controller The host controller, which controls the PD6708, can access the write data (WDB), the read data buffer (RDB), the command register (CMR), and the status register (STR) within the PD6708. 4.1.1 Write data buffer (WDB) WDB is a 4-byte FIFO buffer in which the host controller transmit data and the parameters of the communication control commands are written. 4.1.2 Read data buffer (RDB) RDB is a 20-byte FIFO buffer which stores the receive data acknowledged by the data link layer controller in the PD6708. The host controller reads the PD6708 receive data from RDB. 4.1.3 Command register (CMR) CMR is an 8-bit register used to write control commands for the PD6708. As shown in Table 4-1, the host controller sets the reset mode and the host interface mode in higher 4 bits and sets the communication control command code in lower 4 bits. Table 4-1. Contents of Command Register Bit Bit 7 Value 1 0 Entering the reset mode Exiting the reset mode Meaning Bit 6 1 0 Data of lower 4 bits of CMR is valid. Data of lower 4 bits of CMR is not valid. Change of mode through pin control Data write mode Data read mode Status read mode Set the communication control command codes Switches the host interface mode Bit 5 Bit 4 00 01 10 11 Bit 3 to Bit 0 22 PD6708 4.1.4 Status register (STR) STR is an 8-bit register used to determine the status of the PD6708. The statuses of WDB and RDB and the status of interrupts can be read from higher 4 bits. The return code, which indicates the result of the communication, can be read from lower 4 bits. Table 4-2. Contents of Status Register Bit Bit 7 Value 1 0 Meaning WDB is full WDB is not full RDB is empty RDB is not empty WDB is empty WDB is not empty Interrupt requested Interrupt not requested Return code Description Indicates whether data can be written to WDB Bit 6 1 0 Indicates whether data can be read from RDB Bit 5 1 0 Indicates whether data is in WDB Bit 4 1 0 Indicates whether interrupt servicing is being requested (Bit 4 of the status register is reset by STR by the host controller) Return code will be read Bit 3 to Bit 0 4.2 Host Interface Modes The host controller can access WDB, RDB, CMR, and STR within the PD6708 via the serial interface (SCK, SI, SO). There are four modes for accessing the serial interface, as shown in the Table 4-3. There are two method for switching among these four host interface modes: by using C/D pin and R/W pin, and by writing data to CMR (software control). Table 4-3. Host Interface Mode Mode Data write mode Operation Data input to SI pin is written to WDB from MSB at the rising edge of the serial clock input to SCK pin. Data setting is completed at the eighth serial clock cycle. RDB data is output from MSB to SO pin at the falling edge of the serial clock input to SCK pin. A data read is completed by inputting eight serial clock cycles. Data at SI pin is ignored. Data input to SI pin is written to CMR from MSB at rising edge of the serial clock input to SCK pin. Data setting is completed at the eight serial clock cycle. STR data is output from MSB to SO pin at the falling edge of the serial clock input to SCK pin. A data read is completed by inputting eight serial clock cycles. Data at SI pin is ignored. Data read mode Command write mode Status read mode 23 PD6708 4.2.1 Switching through pin control With bits 5 and 4 of CMR both `0', the host interface mode can be switched by setting the C/D pin and R/W pin to the values shown in Table 4-4. Table 4-4. Switching Host Interface Mode by Pin Control C/D 0 0 1 1 R/W 0 1 0 1 Host Interface Mode Data write mode Data read mode Command write mode Status read mode Figure 4-1. Example of Host Controller Connections by Pin Control 120 IEBus 5V 5V Host Controller PD6708 TEST VDD AVDD BUS+ BUS- SCK SI SO IRQ C/D XO GND R/W Port SCK SO SI INT Port 12 MHz XI CS RESET Port 120 Power Supply Voltage Detection Circuit Caution If the power supply voltage moves out of the 5 V 5 % range, the RESET pin must be driven low for 6 s or more in order to reset the PD6708. 24 Figure 4-2. Host Interface Timing by Pin Control CS C/D R/W SCK SI 00000000 SO Undefined STR Contents Higher 4 bits Lower 4 bits Undefined RDB Contents 0000 Undefined CMR WDB Chip Unselect Command Write Mode Status Read Mode Data Write Mode Data Read Mode PD6708 25 PD6708 4.2.2 Switching through software control With the C/D pin at the high level and the R/W pin at the low level, the host interface mode can be switched from the host controller by setting bits 5 and 4 of CMR to the values shown in Table 4-5. Table 4-5. Switching Host Interface Mode by Software Control Bit 5 0 0 1 1 Bit 4 0 1 0 1 Host Interface Mode Mode switching by pin control Data write mode Data read mode Status read mode After one byte of data has been forwarded, the host interface mode will become the command write mode, which is controlled by the C/D and R/W pins. Figure 4-3. Example of Host Controller Connections by Software Control 120 IEBus 5V 5V Host Controller PD6708 TEST VDD AVDD BUS+ BUS- SCK SI SO IRQ C/D XO GND R/W SCK SO SI INT 12 MHz XI 5V CS RESET 120 Power Supply Voltage Detection Circuit 26 Figure 4-4. Host Interface Timing by Software Control SCK SI 0011 0001 SO Undefined STR Contents Higher 4 bits Undefined 0011 0001 CMR Lower 4 bits WDB Command Write Mode Status Read Mode Command Write Mode Data Write Mode Remark Connect C/D and R/W pins to VDD and GND, respectively. PD6708 27 PD6708 4.3 Reset Mode When the RESET pin is driven low, the PD6708 enters the reset mode. To release the reset mode, the RESET pin must be driven high and a reset release command input. There are two methods of resetting the PD6708, as follows. (1) Resetting with RESET pin If the RESET pin is driven low, the PD6708 will enter the reset mode. To exit the reset mode, drive the RESET pin high and set bit 7 of CMR to `0'. (2) Resetting by software If bit 7 of CMR is set to `1' with the RESET pin fixed high, the PD6708 will enter the reset mode. To exit the reset mode, set bit 7 to `0'. When powering on, the RESET pin must be driven low to execute a reset. The PD6708 will be in the following condition directly after leaving the reset mode. <1> IEBus slave status is intialized. Table 4-6. Slave Status Values after Leaving Reset Mode Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value 1 0 0 0 0 0 0 0 Always `0' Meaning Up to mode 2 is supported The slave transmission section has stopped. Always `0' Unit is not locked. Slave receive buffer is empty. Slave transmit buffer is empty. <2> WDB and RDB are empty. <3> Reception is disabled. Slave reception and broadcast reception are not acknowledged. 28 Figure 4-5. Example of RESET Control on Powering on CS RESET C/D R/W SCK SI 0 0 0 0 0 0 0 0 SO Undefined Higher 4 bits CMR Lower 4 bits Undefined 0000 Power On Reset Mode Command Write Mode PD6708 29 PD6708 5. COMMUNICATION CONTROL COMMANDS The operation conditions of the PD6708 can be controlled by giving it a command from the host controller. After a communication using the appropriate procedure (see 8.3.2 "Communication control command processing routine"), it is executed in a period in which communication is not being performed (standby state). 5.1 Overview of Communication Control Commands Table 5-1. Overview of Communication Control Commands Command Name INIT SETSA MREQ1 MREQ2 ABORT SETSD (Initialize) (Set slave address) (Master request 1) (Master request 2) (Abort) (Set slave data) Description Sets local address and initializes. Sets the unit to communicate with. Communicates as a master unit. Continues in previous condition as the master unit and communicates. Aborts communications. Sets data for slave transmission. Reads communication status. Sets reception disabled state/enabled state. GETSTA (Get status) SETREV (Set receive) (1) Write command The command codes and command parameters for the write commands are shown in Table 5-2. Table 5-2. Command Codes and Command Parameters of Write Commands Command Code (Lower 4 Bits of CMR) 0000 Command Parameters (WDB) First Byte Unit address Second Byte Condition setting code 0000 Master transmit data (first byte) Note Master transmit data (second byte) Note Third Byte Fourth Byte Command Name INIT SETSA MREQ1 0001 0010 Slave address Broad- Control bits Number of master transmit data bytes Note cast bits MREQ2 ABORT SETSD 0011 0100 0101 Number of slave transmit data bytes Reception status code LSB MSB LSB MSB LSB MSB LSB MSB LSB Slave transmit data (first byte) Slave transmit data (second byte) Slave transmit data (third byte) SETREV 0111 MSB Note Only set when transmitting. Caution Note that even if the host controller makes a mistake in setting the number of command parameter bytes, an error message will not be returned by the PD6708, and command processing will be performed as though it were a correctly set command. 30 PD6708 (2) Read command The command code of the read command is shown in Table 5-3. Table 5-3. Command Code of Read Command Command Name Command Code (Lower 4 Bits of CMR) 0110 MSB Data Placed in RDB after Command Execution First Byte Lock status LSB MSB Second Byte GETSTA Address of locked unit (12 bits) LSB LSB MSB Remark With a read command, the command execution result is placed in RDB, and therefore it is performed in the reception disabled state. 5.2 5.2.1 Communication Control Command Functions INIT command (command code: 0000) (1) Functions <1> Unit address setting This command sets the unit address (12 bits), The unit address will be used as the master address when a unit is communicating as the master unit, and as the slave address when a unit is communicating as the slave. <2> Condition setting * The status of bit 4 of IEBus slave status is set. Slave transmission block operation enabled, stopped (bit 4) (Setting of use/non-use of the function that transmits data to the master unit) * The communication mode to be used is set. Table 5-4. Condition Setting Method Condition Setting Code Bits 3 and 2 00 01 10 11 Bit 1 Bit 0 0 0 1 Condition Setting Contents Communication performed in mode 0 Communication performed in mode 1. Communication performed in mode 2. Undefined Fixed at `0' Slave transmission block stopped Slave transmission block operational The local-station address and condition setting contents set by INIT command retain their set values unless power is turned off or reset mode is entered (see 4.3 "Reset Mode"). <3> Slave status initialization The slave status is initialized as shown in Table 5-5. 31 PD6708 Table 5-5. Slave Status after Execution of INIT Command Bit Bit 2 Bit 0 Value 0 0 Meaning Unit is not locked. Slave transmit buffer is empty. <4> Slave transmission and broadcast reception are enabled. <5> After the 2-byte command parameter (master address and condition setting code) have been read from the write data buffer (WDB), WDB is cleared. (2) Example When INIT command specifies that the master address is `012H' and the condition setting are `communication in mode 1' and `slave data transmission section operable', the contents of WDB and CMR are as shown below. First Byte WDB 0000 0001 Master Address Second Byte 0010 0101 Condition Setting Code Third Byte Fourth Byte CMR 0100 0000 5.2.2 SETSA command (command code: 0001) (1) Functions <1> Slave address (12 bits) setting The value for the slave address set by the SETSA command remains unchanged until the power is turned off or the reset mode is entered. <2> This command clears WDB after reading the 2-byte command parameter (slave address) from WDB. (2) Example When SETSA command sets the slave address as `024H', the contents of WDB and CMR are as shown below. First Byte WDB 0000 0010 Slave Address Second Byte 0100 0000 Set to 0000 Third Byte Fourth Byte CMR 0100 0001 32 PD6708 5.2.3 MREQ1 command (command code: 0010) (1) Functions This command executes a master communication (transmission or reception). After execution of the command, the unit begins communication as the master unit. As long as it does not lose in arbitration, the master unit will communicate with the slave unit which has the slave address specified by SETSA command. <1> Selected broadcast communication or ordinary communication Broadcast communication selection Ordinary communication selection : 0H (broadcast bit `0' output) : 8H (broadcast bit `1' output) <2> Sets the control bits (4 bits) <3> Sets the number of transmit data bytes (8 bits) (transmission only) Table 5-6. Number of Transmit Data Bytes Setting Number of Transmit Data Bytes 1 byte 2 bytes : : 255 bytes 256 bytes Command Parameter 1H 2H : : FFH 00H <4> Sets the transmit data (transmission only) (2) Example When the MREQ1 command is used to select `ordinary communication', set the control bit to `AH' (command write and lock), the number of transmit data bytes to 4, and the transmit data to 12H, 34H, 56H, and 78H, the contents of WDB and CMR are shown below. First Byte WDB 1000 Broadcast Bits CMR 0100 1010 Control Bits 0010 Second Byte 0000 0100 Third Byte 0001 0010 First Data Byte Fourth Byte 0011 0100 Second Data Byte Number of Transmit Data Bytes Caution Transmit data 56H and 78H should be set when the above command parameters have been read and WDB is empty. 33 PD6708 5.2.4 MREQ2 command (command code: 0011) (1) Functions This command re-executes a master communication (transmission or reception). If master transmission or reception stops midway, the master communication is re-executed from the stopped condition. (2) Command execution conditions If a communication control command other than an MREQ2 command is executed after the master communication ends midway, the MREQ1 command may not re-execute the communication correctly from the communication interrupted condition. (3) Example When re-execution is performed by the MREQ2 command when communication has been interrupted due to generation of a timing error after transmission of two bytes (12H and 34H) in mode 1, as in the MREQ1 command example, the contents of WDB and CMR are as shown below. First Byte WDB 0101 0110 Second Byte 0111 1000 Third Byte Fourth Byte Data to be Transmitted upon Re-Execution of Command CMR 0100 0011 The previously set MREQ1 command values are used for the broadcast bits, control bits and number of transmit data bytes. Cautions 1. A master communication performed by execution of the MREQ1 and MREQ2 commands is performed in only one frame. However, if the unit loses in arbitration, the frame is automatically reset up twice (three times in total). 2. INIT command must be executed before setting the MREQ1 or MREQ2 command. If MREQ1 or MREQ2 is set before execution of INIT command, master communication will not be performed. 5.2.5 ABORT command (command code: 0100) (1) Functions This command aborts master communications and slave unit data transmissions. <1> It clears the data placed in WDB. <2> It cancels the slave transmit data (SETSD command). (2) Example When the master unit begins communication as in the MREQ1 command example, a communication error is generated and the two bytes of transmit data (12H and 34H) remaining in WDB are canceled by ABORT command, the contents of CMR are as shown below. 34 PD6708 [Before execution of ABORT command] First Byte WDB 0001 0010 Second Byte 0011 0100 Third Byte Fourth Byte CMR 0100 0100 [After execution of ABORT command] First Byte WDB Second Byte Third Byte Fourth Byte CMR The data placed in WDB is cleared. 5.2.6 SETSD command (command code: 0101) (1) Functions This command specifies the data transmitted to the master unit when a `data read and lock' (control bits: 3H) or a `data read' (control bits: 7H) is received from the master unit. <1> Sets the number transmit data bytes (8 bits) Table 5-7. Number of Transmit Data Bytes Number of Transmit Data Bytes 1 byte 2 bytes : : 64 bytes Command Parameter 1H 2H : : 40H <2> Sets the transmit data 35 PD6708 (2) Validity of SETSD command When SETSD command is executed, it remains valid until one of the following cases arises. * `Data read and lock' (control bits: 3H) or `data read' (control bits: 7H) is received from the master unit. * ABORT command is executed. * Power is turned off, or the reset mode is entered. When the SETSD command is valid, WDB functions as the slave transmit buffer. Caution The SETSD command can be executed even if the unit is placed in the slave transmission selection halted state by INIT command. (3) Example When the SETSD command is used to set the number of transmit data bytes to 5, and the transmit data to ABH, CDH, EFH, 14H, and 25H, the contents of WDB and CMR are as shown below. First Byte WDB 0000 0101 Second Byte 1010 1011 Third Byte 1100 1101 Second Data Byte Fourth Byte 1110 1111 Third Data Byte Number of Transmit Data Bytes CMR 0100 0101 First Data Byte Caution Transmit data 14H and 25H should be set when the above command parameters have been read and WDB is empty. 5.2.7 GETSTA command (command code: 0110) The GETSTA command is used by a unit to check whether it is locked by another unit. (1) Functions <1> Reads the lock status which indicates whether or not this unit is locked by another unit. `1J' is placed in RDB if the unit is locked, and `0H' if not locked. <2> The address (12 bits) of a locked unit is placed in RDB. This data is meaningless when the unit is not locked. After execution of GETSTA command, the data placed in RDB is as follows. First Byte Lock Status MSB Second Byte Address of Locked Unit (12 Bits) LSB 36 PD6708 (2) Command setting conditions The reception disabled state must be set and RDB emptied before setting the GETSTA command. Caution With the IEBus, the lock function is provided to enable communication to run over a number of frames. However, if a locked unit goes down without being unlocked, the locked unit is unable to receive any further data. To avoid this situation, in a system which uses the lock function it is necessary to execute the GETSTA command periodically to monitor the lock status (a unit lock is released by executing INIT command). 5.2.8 SETREV command (command code: 0111) (1) Functions <1> Set reception enabled/disabled status * When reception status code is 00H : Set to reception disabled status. In the reception disabled status, bit 1 of the slave status is `1', the slave receive buffer becomes virtually empty and no longer exists, and slave reception and broadcast reception are no longer performed. * When reception status code is 01H : Set to reception enabled status. When the prescribed conditions are met, slave reception and broadcast reception are performed. The reception enabled status is also set when a command other than SETREV is executed. <2> This command clears WDB after reading the 1-byte command parameter (reception status code) from WDB. 37 PD6708 6. RETURN CODES The PD6708 sets the communication status as a return code in lower 4 bits of the status register (STR) and requests an interrupt (IRQ output). As a result of the interrupt request from the PD6708, the host controller can ascertain the communication result by reading the return code in the status read mode. 6.1 Return Codes in Master/Slave Data Transmission Table 6-1 shows the return codes placed in the status register when a unit has executed the MREQ1 or MREQ2 command and becomes the master unit (including broadcast communication), and when the SETSD command is executed and the slave unit transmits data. Table 6-1. Return Codes in Master/Slave Transmission Return Code Name Transmission start Code 0000 Description Indicates that master/slave transmission will start. The point of generation differs between master transmission and slave transmission. <1> Master transmission Set when the master address field ends and the unit wins as the master unit. <2> Slave transmission Set when control bits (3H, 7H) which request data transmission are received from the master unit. Indicates that transmission of the number of data bytes specified by the message length bits has ended within one frame. Indicates that the communication has ended without completion of transmission of the number of data bytes specified by the message length bits within one frame. In master transmission, termination during transmission is not flagged if the unit loses once in arbitration, and transmission is attempted up to three times. Transmission normal termination 0010 Termination during transmission 0011 6.2 Return Codes in Master Reception Table 6-2 shows the return codes placed in STR when a unit has executed the MREQ1 or MREQ2 command and becomes the master unit, and receives data, a status or lock address from a slave unit. 38 PD6708 Table 6-2. Return Codes in Master Reception Return Code Name Master reception start Code 0100 Description This return code is generated when the master unit correctly receives the message length code from the slave unit, informing the host controller of the start of master reception. Each time 20 bytes (RDB capacity) of master receive data is received, if RDB is full, this return code makes a request to the host controller for a read of receive data from RDB. Indicates that reception of the number of data bytes specified by the message length bits has ended within one frame. Indicates that the communication has ended without completion of transmission of the number of data bytes specified by the message length bits within one frame. Termination during master reception is not flagged if the unit loses once in arbitration, and reception is attempted up to three times. Master receive data full 0101 Master reception normal termination Termination during master reception 0110 0111 6.3 Return Codes in Slave Reception Table 6-3 shows the return codes placed in STR when data or a command is received from the master unit. Table 6-3. Return Codes in Slave Reception Return Code Name Slave reception start Code 1000 Description This return code is generated when the slave unit correctly receives the message length codes from the master unit, informing the host controller of the start of slave reception. Each time 20 bytes (RDB capacity) of slave receive data is received, if RDB is full, this return code makes a request to the host controller for a read of receive data from RDB. Indicates that reception of the number of data bytes specified by the message length bits has ended within one frame. Indicates that the communication has ended without completion of transmission of the number of data bytes specified by the message length bits within one frame. Slave receive data full 1001 Slave reception normal termination Termination during slave reception 1010 1011 6.4 Return Codes in Broadcast Reception Table 6-4 shows the return codes placed in STR when data or a command is received from the master unit in broadcast communication. 39 PD6708 Table 6-4. Return Codes in Broadcast Reception Return Code Name Broadcast reception start Code 1100 Description This return code is generated when the slave unit correctly receives the message length codes from the master unit, informing the host controller of the start of slave reception. Each time 20 bytes (RDB capacity) of slave receive data is received, if RDB is full, this return code makes a request to the host controller for a read of receive data from RDB. Indicates that reception of the number of data bytes specified by the message length bits has ended within one frame. Indicates that the communication has ended without completion of transmission of the number of data bytes specified by the message length bits within one frame. Broadcast receive data full 1101 Broadcast reception normal termination Termination during broadcast reception 1110 1111 6.5 Return Codes Generation Intervals This section describes the generation order and the minimum generation interval for return codes generated each time communication is performed, Each time a new return code is generated, it is placed in STR without regard to STR read. For this reason, the host controller must take account of the minimum return code generation interval in controlling the PD6708. (1) Master transmission After execution of the MREQ1 or MREQ2 command, the order of generation of master transmission return codes is as shown in Figure 6-1. Figure 6-1. Return Code Generation Order in Master Transmission Transmission Normal Termination (Return Code : 0010) Termination During Transmission (Return Code : 0011) T1 Transmission Start (Return Code : 0000) T2 T3 New communication return codes * Slave reception start (Return code : 1000) T3 Termination During Transmission (Return Code : 0011) * Broadcast reception start (Return code : 1100) etc. T3 The minimum generation intervals for return codes in master transmission are shown below. Table 6-5. Minimum Generation Intervals for Return Codes in Master Transmission (s) Time T1 T2 T3 Mode 0 Approx. 6325 Approx. 10 Approx. 7290 Mode 1 Approx. 1605 Approx. 10 Approx. 2050 Mode 2 Approx. 1160 Approx. 10 Approx. 1550 40 PD6708 (2) Slave transmission After execution of the SETSD command, the order of generation of slave transmission return codes is as shown in Figure 6-2. Figure 6-2. Return Code Generation Order in Slave Transmission Transmission Normal Termination (Return Code : 0010) Termination During Transmission (Return Code : 0011) T1 Transmission Start (Return Code : 0000) T2 T3 New communication return codes * Slave reception start (Return code : 1000) T3 * Broadcast reception start (Return code : 1100) etc. The minimum generation intervals for return codes in slave transmission are shown below. Table 6-6. Minimum Generation Intervals for Return Codes in Slave Transmission (s) Time T1 T2 T3 Mode 0 Approx. 1580 Approx. 10 Approx. 7290 Mode 1 Approx. 400 Approx. 10 Approx. 2050 Mode 2 Approx. 290 Approx. 10 Approx. 1550 (3) Master reception After execution of the MREQ1 or MREQ2 command, the order of generation of master reception returns codes is as shown in Figure 6-3. Figure 6-3. Return Code Generation Order in Master Reception Master Receive Buffer Full (Return Code : 0101) Master Reception Normal Termination (Return Code : 0110) Termination During Master Reception (Return Code : 0111) T1 Master Receive Buffer Full (Return Code : 0101) T1 Master Reception Start (Return Code : 0100) Master Reception Normal Termination (Return Code : 0110) Termination During Master Reception (Return Code : 0111) T2 T3 T4 New communication return codes * Slave reception start (Return code : 1000) * Broadcast reception start (Return code : 1100) etc. T4 T2 T4 T3 T4 Termination During Master Reception (Return Code : 0111) T4 The minimum generation intervals for return codes in master transmission are shown below. 41 PD6708 Table 6-7. Minimum Generation Intervals for Return Codes in Master Reception (s) Time T1 T2 T3 T4 Mode 0 Note Approx. 1580 Approx. 10 Approx. 7290 Mode 1 Approx. 8030 Approx. 400 Approx. 10 Approx. 2050 Mode 2 Approx. 5800 Approx. 290 Approx. 10 Approx. 1550 Note The mode 0 master receive data consists of up to 19 bytes. Therefore, the receive buffer (20 bytes) does not become full, and a return code is not generated. (4) Slave reception The order of generation of slave reception return codes is as shown in Figure 6-4. Figure 6-4. Return Code Generation Order in Slave Reception Slave Receive Buffer Full (Return Code : 1001) Slave Reception Normal Termination (Return Code : 1010) Termination During Slave Reception (Return Code : 1011) T1 Slave Receive Buffer Full (Return Code : 1001) T1 Slave Reception Start (Return Code : 1000) T2 T3 T4 New communication return codes * Slave reception start (Return code : 1000) * Broadcast reception start (Return code : 1100) etc. T4 T2 Slave Reception Normal Termination (Return Code : 1010) Termination During Slave Reception (Return Code : 1011) T4 T3 T4 The minimum generation intervals for return codes in master transmission are shown below. Table 6-8. Minimum Generation Intervals for Return Codes in Slave Reception (s) Time T1 T2 T3 T4 Mode 0 Note Approx. 1580 Approx. 10 Approx. 7290 Mode 1 Approx. 8030 Approx. 400 Approx. 10 Approx. 2050 Mode 2 Approx. 5800 Approx. 290 Approx. 10 Approx. 1550 Note The mode 0 master receive data consists of up to 19 bytes. Therefore, the receive buffer (20 bytes) does not become full, and a return code is not generated. (5) Broadcast reception The return code generation order and minimum generation intervals in the case of broadcast reception are the same as for (4) Slave reception as shown above. 42 PD6708 7. COMMUNICATING WITH HOST CONTROLLER This section explains the flow of data between the PD6708 and the host controller via the serial interface (SCK, SO, SI pins) during communications. 7.1 Master Transmission Master transmission is the communication data exchange which takes place when a unit becomes a master unit by specifying AH, BH, and FH as control bits and executing the MREQ1 or MREQ2 command, and then transmitting data and commands to slave units. 7.1.1 Master transmission by MREQ1 command (1) The control bits, number of transmit data bytes and transmit data are placed in the write WDB as command parameters as shown in Figure 7-1, and the MREQ1 command (command code: 2H) is executed. (2) When a unit wins in arbitration as the master unit (the end of the master address field), the transmission start return code (0H) is placed in the status register (STR), and an interrupt request is generated for the host controller. At this time, the host controller places the third and following bytes of transmit data in WDB. Figure 7-1. Data Exchange During Master Transmission (Contents of WDB) First Byte WDB Broadcast Bits Control Bits Second Byte Number of Transmit Data Bytes Third Byte Fourth Byte Transmit Data (First Byte) Transmit Data (Second Byte) (3) If the number of data or command bytes specified by "number of transmit data bytes" are transmitted correctly, a "transmission end" return code (2H) will be placed in STR and an interrupt request will be generated. (4) If an error occurs during transmission and the data communication is halted, a "termination during transmission" return code (3H) will be placed in STR and an interrupt request will be generated. The timing at which the PD6708 reads transmit data from WDB is shown below. Table 7-1. Timing for Reading Transmit Data from WDB (The minimum time after transmission start return code (0H) is set in STR) Timing for Reading Transmit Data from WDB (s) Transmit Data Mode 0 Transmit data (first byte) Transmit data (second byte) : Transmit data (N-th byte) Approx. 4745 Approx. 6325 : Approx. 3165+1580 x N Mode 1 Approx. 1205 Approx. 1605 : Approx. 805+400 x N Mode 2 Approx. 870 Approx. 1160 : Approx. 580+290 x N 43 PD6708 7.1.2 Master transmission by MREQ2 command If the MREQ1 command is executed and a communication error occurs during the transmission of data or a command, with the result that not all the data is transmitted, the remaining data can be transmitted by executing the MREQ2 command. (1) The remaining data is placed in WDB as command parameters as shown in Figure 7-2, and the MREQ2 command (command code: 3H) is executed. Figure 7-2. Data Exchange During Master Transmission (Contents of Write Data Buffer) First Byte WDB Transmit Data (N-th Byte) Second Byte Transmit Data (Byte N+1) Third Byte Transmit Data (Byte N+2) Fourth Byte Transmit Data (Byte N+3) The remaining operations are the same as 7.1.1 "Master transmission by MREQ1 command". 7.2 Slave Transmission 7.2.1 Data transmission When the slave unit receives control bit 3H or 7H from the master unit, it transmits data as follows. (1) It places the number of transmit data bytes and transmit data in WDB as command parameters as shown in Figure 7-3, and executes the SETSD command (command code: 5H). (2) When the unit receives control bit 3H or 7H from the master unit, the "transmission start" return code (0H) is placed in STR, and an interrupt request is generated. At this time, the host controller places the fourth and following bytes of transmit data in WDB. Figure 7-3. Data Exchange During Slave Transmission (Contents of WDB) First Byte WDB Number of Transmit Data Bytes Second Byte Third Byte Fourth Byte Transmit Data (First Byte) Transmit Data (Second Byte) Transmit Data (Third Byte) (3) If the number of data or command bytes specified by "number of transmit data bytes" is transmitted correctly, a "transmission end" return code (2H) will be placed in STR and an interrupt request will be generated. (4) If an error occurs during transmission and the data communication is halted, a "termination during transmission" return code (3H) will be placed in STR and an interrupt request will be generated. The timing at which the PD6708 reads transmit data from WDB is shown below. 44 PD6708 Table 7-2. Timing for Reading Transmit Data from WDB (The minimum time after transmission start return code (0H) is set) Timing for Reading Transmit Data from WDB (s) Transmit Data Mode 0 Transmit data (first byte) Transmit data (second byte) : Transmit data (N-th byte) Approx. 1580 Approx. 3160 : Approx. 1580 x N Mode 1 Approx. 400 Approx. 800 : Approx. 400 x N Mode 2 Approx. 290 Approx. 580 : Approx. 290 x N 7.2.2 Transmitting slave status address and lock address When the PD6708 receives 0H, 4H, 5H, and 6H as control bits from the master unit, the slave status and lock address are generated automatically and sent to the master unit. As a result, there is no necessity for the host controller to be involved in the transmission of the slave status and lock address. 7.3 Master Reception When a unit becomes a master unit by setting 0H, 3H, 4H, 5H, 6H, and 7H as control bits and executing the MREQ1 or MREQ2 command, and receives data, slave status and lock address from the slave unit, the following will occur. (1) When the master unit returns an acknowledge in the message length field, the slave address, control bits and message length bits are placed in the read data buffer (RDB) by the MREQ1 command as shown in Figure 7-4, the "master reception start" return code (6H) is placed in STR, and an interrupt request is generated. Figure 7-4. Data Exchange During Master Reception (Contents of RDB) First Byte RDB Slave Address (12 Bits) Second Byte Control Bits Third Byte Message Length Bits Fourth Byte Onward (2) Each time one byte of receive data is received, it is placed in RDB. (3) Each time 20 bytes (RDB capacity) of receive data are received, if RDB is full, a "master receive buffer full" return code (5H) is placed in STR, and an interrupt request is generated. (4) After one frame of data is placed in RDB, a "master reception normal termination" return code (6H) is placed in STR and an interrupt request is generated. (5) If a communication error occurs during reception and communication stops without receiving all of the data transmitted from the slave unit, a "termination during master reception" return code (7H) is placed in STR and an interrupt request is generated. The areas where PD6708 places receive data, etc., in RDB are shown below. 45 PD6708 Table 7-3. Placing Receive Data in RDB Time (s) Areas where RDB is read Mode 0 When ACK bit is transmitted in message length field 0 Mode 1 0 Mode 2 0 Note Parameter/ Communication Data Slave address Control bits Message length bits Receive data (first byte) Receive data (second byte) Receive data (N-th byte) When first ACK bit is transmitted in data field When second ACK bit is transmitted in data field When N-th ACK bit is transmitted in data field Approx. 1580 Approx. 3160 Approx. 400 Approx. 800 Approx. 290 Approx. 580 Approx. 290 x N Approx. 1580 x N Approx. 400 x N Note 7.4 Minimum time after the "master reception start" return code is placed in STR and an interrupt request is generated. Slave Reception If a slave unit receives AH, BH, EH, or FH as control bits from the master unit and receive data or a command, the following will occur. (1) When the slave unit returns an acknowledge in the message length field, the master address, control bits and message length bits are placed in RDB as shown in Figure 7-5, a " slave reception start" return code (8H) is placed in STR, and an interrupt request is generated. Figure 7-5. Data Exchange During Slave Reception (Contents of RDB) First Byte RDB Master Address (12 Bits) Second Byte Control Bits Third Byte Message Length Bits Fourth Byte Onward (2) Each time one byte of receive data is received, it is placed in RDB. (3) Each time 20 bytes (RDB capacity) of receive data are received, if RDB is full, a "slave receive buffer full" return code (9H) is placed in STR, and an interrupt request is generated. (4) After the final data of one frame is placed in RDB, a "slave reception normal termination" return code (AH) is placed in STR and an interrupt request is generated. (5) If a communication error occurs during reception and communication stops without receiving all of the data transmitted from the master unit, a "termination during slave reception" return code (BH) is placed in STR and an interrupt request is generated. The areas where the PD6708 places receive data, etc., in RDB are shown below. 46 PD6708 Table 7-4. Placing Receive Data in RDB Parameter/ Communication Data Master address Control bits Message length bits Receive data (first byte) Receive data (second byte) Receive data (N-th byte) When first ACK bit is received in data field When second ACK bit is received in data field When N-th ACK bit is received in data field Approx. 1580 Approx. 3160 Approx. 400 Approx. 800 Approx. 290 Approx. 580 Approx. 290 x N Time (s) Areas where RDB is read Mode 0 When ACK bit is received in message length field 0 Mode 1 0 Mode 2 0 Note Approx. 1580 x N Approx. 400 x N Note 7.5 Minimum time after the "slave reception start" return code is placed in STR and an interrupt request is generated. Broadcast Reception (1) When a broadcast reception unit receives the message length field, the master address, control bits and message length bits are placed in RDB as shown in Figure 7-6, a "broadcast reception start" return code (CH) is placed in STR, and an interrupt request is generated. Figure 7-6. Data Exchange During Broadcast Reception (Contents of RDB) First Byte RDB Master Address (12 Bits) Second Byte Control Bits Third Byte Message Length Bits Fourth Byte Onward (2) Each time one byte of receive data is received, it is placed in RDB. (3) Each time 20 bytes (RDB capacity) of receive data are received, if RDB is full, a "slave receive buffer full" return code (DH) is placed in STR, and an interrupt request is generated. (4) After the final data of one frame is placed in RDB, a "broadcast reception normal termination" return code (EH) is placed in STR and an interrupt request is generated. (5) If a communication error occurs during reception and communication stops without receiving all of the data transmitted from the master unit, a "termination during broadcast reception" return code (FH) is placed in STR and an interrupt request is generated. The areas where the PD6708 places receive data, etc., in RDB are the same as those shown in Table 7-4. 47 PD6708 8. EXAMPLE OF HOST CONTROLLER PROCESSING FLOW This chapter presents an example of the host controller processing flow for controlling the PD6708 via the serial interface (SCK, SO, and SI pins). The host controller processing flow comprises the following routines. * Main routine * Interrupt service routine 8.1 Main Routine Start Equipment initialization PD6708 initialization routine See 8.3.1 Crq Note 0 1 Command processing routine See 8.3.2 Normal End Equipment control routine Note Note The equipment control routine is a routine which performs host controller application processing. When controlling the PD6708, set the Crq flag when there is a command request. 48 Exit PD6708 8.2 Interrupt Service Routine This routine is used when an interrupt request is generated from the PD6708 (when IRQ pin becomes high). This routine reads the contents of the return code, performs flag setting, and reads receive data. Start Disable interrupts from PD6708 Y Is SIO register used? This processing is not necessary if interrupts are disabled when SIO is used in the main routine. N Save value of I/O port which controls PD6708 C/D and R/W pins, and value of SIO register in host controller Read STR Most significant 2 bits of return code 00 Return code classification 01 10 11 Y Master? N Master transmission processing routine Note 1 Slave data transmission processing routine Note 2 Master reception processing routine Note 3 Slave reception processing routine Broadcast reception processing routine Restore value of I/O port which controls PD6708 C/D and R/W pins, and value of SIO register in host controller Notes 1. See 8.3.3. 2. See 8.3.4. 3. See 8.3.5. Enable interrupts from PD6708 RETI End 49 PD6708 8.3 8.3.1 Processing Routine PD6708 initialization routine Start Reset PD6708 Drive the host controller port which controls the PD6708 RESET pin low for 6 s or longer, then return it to high. (Not necessary when a hardware reset such as a power-on reset is executed.) CMR 00H Place 00H in the command register. Release reset mode. INIT command setting Set unit address slave unit condition with INIT command. Normal end * INIT command setting flow Start Read STR N WDB empty? Y EXIT Write to WDB Unit Address Setting (Higher 8 Bits) Write to WDB Unit Address (Lower 4 Bits) Slave Unit Condition Setting Write to CMR Set command code (0H). Normal end 50 PD6708 8.3.2 Communication control command processing routine This processing routine sets the PD6708 communication control commands SETSA, MREQ1, MREQ2, ABORT, GETSA, and SETREV. Processing starts when there is a command request during equipment control (Crq = 1) (1) SETSA command Start Read STR N WDB empty? Y EXIT Write to WDB Slave Address Setting (Higher 8 Bits) Write to WDB Slave Address (Lower 4 Bits) Communication Mode Setting Write to CMR Set command code (1H). Normal end 51 PD6708 (2) MREQ1 command When MSB of the control bits is 1 (master transmission) Start Read STR N WDB empty? Y EXIT Write to WDB Set broadcast bits and control bits. Write to WDB Set number of master transmit data bytes. Write to WDB Set master transmit data (first byte). Write to WDB Set master transmit data (second byte). N1 (Number of master transmit data bytes) - 2 Write to CMR Set command code (2H). Normal end 52 PD6708 (3) MREQ2 command After master transmission ends midway Start Read STR WDB full? Y Write to CMR N Write to WDB Set master transmit data. Set command code (3H). Normal end (4) MREQ1 command When MSB of the control bits is 0 (master reception) Start Read STR N WDB and RDB empty? EXIT Y Write to WDB Set broadcast bits and control bits. Write to CMR Set command code (2H). Normal end 53 PD6708 (5) MREQ2 command When master reception ends midway Start Read STR N WDB and RDB empty? EXIT Y Write to CMR Set command code (3H). Normal end (6) ABORT command Start Write to CMR Set command code (4H). Normal end 54 PD6708 (7) SETSD command Start Read STR N WDB empty? Y EXIT Write to WDB Set number of slave transmit data bytes. Write to WDB Set slave transmit data (first byte). Write to WDB Set slave transmit data (second byte). Write to WDB Set slave transmit data (third byte). N2 (Number of slave transmit data bytes) - 3 Write to CMR Set command code (5H). Slave transmission timer setting If the slave data transmission processing shown in 8.3.4 cannot be completed because control bits (3H, 7H) requesting slave data transmission were not received from the master unit within the prescribed time, an ABORT command is executed and slave data transmission is exited. Normal end 55 PD6708 (8) GETSTA command Start Read STR N WDB empty? Y Write to WDB Set reception status code (reception disabled : 00H). Write to CMR Set SETREV command code (7H). Read STR N WDB and RDB empty? Y EXIT Write to CMR Set GETSTA command code (6H). Read STR RDB empty? N Read RDB Y Read lock status (4 bits) and lock address (higher 4 bits). Read RDB Read lock address (higher 8 bits). Normal end 56 PD6708 8.3.3 Master transmission processing routine This processing routine is used when a unit becomes the master unit after executing the MREQ1 or MREQ2 command and transmits data and commands to a slave unit. This routine is an interrupt service routine, and is executed when the return code (higher 2 bits = 00) is read in master transmission. Start Read STR Y Return code 3H? N Note 1 Note 2 Termination during transmission N1 = 0 Y N WDB full? N Write to WDB Y Set master transmit data. Note 2 N1 N1 - 1 Return code 2H? N Y Normal end Notes 1. To transmit the remaining data, execute the MREQ2 command (see 8.3.2 (3)). To abort master transmission, execute the ABORT command (see 8.3.2 (6)). 2. N1: Number of master transmit data bytes. 57 PD6708 8.3.4 Slave data transmission processing routine This processing routine is used when a slave unit transmits data to the master unit after setting the SETSD command. This routine is an interrupt service routine, and is executed when the return code (higher 2 bits = 00) is read in slave data transmission. Start Read STR Y Return code 3H? N Note 1 Note 2 Termination during transmission N2 = 0 Y N WDB full? N Write to WDB Y Set slave transmit data. Note 2 N2 N2 - 2 Return code 2H? N Y Normal end Notes 1. Untransmitted data in WDB is cleared by executing the ABORT command (see 8.3.2 (6)). 2. N2: Number of slave transmit data bytes 58 PD6708 8.3.5 Master reception processing routine This processing routine is used when the master unit receive data, slave status and lock address after execution of the MREQ1 or MREQ2 command. One of four different routines is executed depending on the contents of the return code. (1) Processing in case of master reception start return code (4H) Start Mre 1 Set master reception flag (Mre). Read RDB Read slave address (higher 8 bits). Read RDB Read slave address (lower 4 bits) and control bits. Read RDB Read number of master receive data bytes. N3 Number of master receive data bytes Normal end 59 PD6708 (2) Processing in case of master receive buffer full return code (5H) Start I 20 Set master receive buffer size. II-1 I=0? Y N END Read RDB Read master receive data. Note N3 N3 - 1 Note N3: Number of master receive data bytes 60 PD6708 (3) Processing in case of master reception normal end return code (6H) Start Y Mre = 1 ? N Mre 1 Set master reception flag (Mre). Read RDB Read slave address (higher 8 bits). Read RDB Read slave address (lower 4 bits) and control bits. Read RDB Read number of master receive data bytes. N3 number of master receive data bytes Read RDB Read master receive data. N3 N3 - 1 N N3 = 0 ? Y Mre 0 End 61 PD6708 (4) Processing in case of end during master reception return code (7H) Start Y Mre = 1 ? N Mre 1 Set master reception flag (Mre). Read RDB Read slave address (higher 8 bits). Read RDB Read slave address (lower 4 bits) and control bits. Read RDB Read number of master receive data bytes. N3 number of master receive data bytes Read STR Note RDB empty ? N Read RDB Y Mre 0 Read master receive data. End Note To distinguish data from receive data (slave reception, broadcast reception) newly input in the next communication frame, after reading RDB (inputting one serial clock pulse to SCK pin), STR should be read (inputting one serial clock pulse to SCK pin) within the time shown below. * When the next frame is mode 2 * When the next frame is mode 1 : Approx. 290 s : Approx. 400 s * When the next frame is mode 0 : Approx. 1580 s However, the above time limits for reading STR do not apply if this processing routine is executed in the reception disabled state after executing the SETREV command. The flowcharts for slave reception processing and broadcast reception processing are the same as for master reception processing, and are therefore omitted here. 62 PD6708 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) PARAMETER Power supply Logic input voltage Logic output voltage Bus input voltage Bus output voltage Operating ambient temperature Storage temperature SYMBOL VDD, AVDD VI The pin without BUS+ and BUS- VO VBI BUS+ and BUS- VBO TA Tstg -0.5 to + 6.0 -40 to + 85 -65 to + 150 V C C -0.5 to VDD + 0.3 -0.5 to + 6.0 V V TEST CONDITIONS | VDD - AVDD | < 0.5 V RATINGS -0.5 to +7.0 -0.5 to VDD + 0.3 UNIT V V DC Characteristics (TA = -40 to +85 C, VDD = AVDD = 5 V 10 %) PARAMETER Input voltage high Input voltage low Output voltage high Output voltage low Input leakage current high Input leakage current low Output leakage current high Output leakage current low Supply current IDD2 Reset mode 1.2 3 mA SYMBOL VIH VIL VOH VOL ILIH ILIL ILOH ILOL IDD1 IOH = -400 A IOL = 2.5 mA VI = VDD VI = 0 V VO = VDD VO = 0 V Carrier sense 3.5 TEST CONDITIONS MIN. 0.8VDD 0 0.7VDD 0.4 10 -10 10 -10 10 TYP. MAX. VDD 0.2VDD UNIT V V V V A A A A mA Capacitance Characteristics (TA = 25 C, VDD = AVDD = 0 V) PARAMETER Input capacitance Input/output capacitance SYMBOL CI CIO TEST CONDITIONS fc = 1 MHz, unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 UNIT pF pF 63 PD6708 Recommended Ceramic Resonator (12 MHz) External Capacities [pF] Manufacturer Murata Mfg. Product Name C1 CST12.0MT Note 1 Recommended Crystal Resonator (12 MHz) External Capacities [pF] Manufacturer C2 -- 30 33 Kinseki, Ltd HC-49/U Product Name C1 22 C2 22 -- 30 33 CSA12.00MX241 Kyocera Corp. KBR-12.0M Note 2 5 Recommended Ceramic Resonator (12.58 MHz) External Capacities [pF] Manufacturer Murata Mfg. TDK Product Name C1 CSTCS12.5MTA 904 Note 1 C2 -- 33 -- 33 FCR12.58M2S Note 1 Notes 1. Can only be used when communication mode 0 or 1 is used (frequency accuracy: 1.5 %). 2. This is a custom product, and therefore the manufacturer should be contacted directly. 5 Caution The oscillation circuit constants and oscillation voltage range shown above indicate the condition under which oscillation is stable and do not guarantee the oscillation frequency accuracy. If a high oscillation frequency accuracy is required from the actual circuit, the resonator mounted to the actual circuit must be adjusted. For details, directly consult the manufacturer of the resonator. 5 External Circuit XI XO GND C1 C2 Caution Wire the dotted portion in the above figure as follows to prevent adverse influences of wiring capacitance when using the system clock oscillation circuit. * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. * Do not place the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. * Do not ground the wiring to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 64 PD6708 AC Characteristics (TA = -40 to +85 C, VDD = AVDD = 5 V 10 %) PARAMETER System clock SYMBOL TEST CONDITIONS fX = 12 MHz Using communication mode 2 Using communication mode 0,1 fX = 12.58 MHz Using communication mode 2 Using communication mode 0,1 MIN. 11.94 11.82 12.52 12.40 0.8 0.4 0.4 100 400 TYP. 12.00 12.00 12.58 12.58 MAX. 12.06 12.18 12.64 12.76 UNIT MHz MHz MHz MHz SCK cycle time SCK high-level width SCK low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time (from SCK) CS, C/D, R/W setup time (to SCK) CS, C/D, R/W hold time (from SCK) CS high-level width IRQ output high-level width RESET low-level width Oscillation stabilization time tKCY tKH tKL tSIK tKSI tKSO tSA tHA s s s ns ns 300 ns ns ns ns 11 0 400 400 8 6 s s ms tOS fX = 12 MHz 20 Serial Transfer Timing tSA tHA CS, C/D, R/W tKYC tKL tKH SCK tSIK tKSI SI Data Input tKSO SO Data Output 65 PD6708 IEBus Driver/Receiver Characteristics (TA = -40 to +85 C, VDD = AVDD = 5 V 10 %) PARAMETER Output current high Output current low In-phase output voltage Input voltage high Input voltage low Input hysteresis voltage In-phase input voltage high In-phase input voltage low Driver output resistance Driver output capacitance Receiver input capacitance SYMBOL IOH IOL VOCOM VIH VIL VIHYS VIHCOM VILCOM RO CO CI Between BUS + and BUS - Between BUS + and BUS -, Between BUS + and GND, Between BUS - and GND 1.00 0 100 25 25 25 VDD - 1.0 VDD When high and low VDD -0.25 2 120 20.0 VDD 2 TEST CONDITIONS RL = 60 5 % MIN. - 2.73 TYP. MAX. - 6.22 1.0 VDD +0.25 2 UNIT mA A V mV mV mV V V k pF pF 66 PD6708 10. PACKAGE DRAWINGS 16 PIN PLASTIC DIP (300 mil) 16 9 5 1 A 8 K P L J I G H F C D N M B M R NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N P R MILLIMETERS 20.32 MAX. 1.27 MAX. 2.54 (T.P.) 0.500.10 1.1 MIN. 3.50.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 7.62 (T.P.) 6.5 0.25 +0.10 -0.05 0.25 1.1 MIN. 015 INCHES 0.800 MAX. 0.050 MAX. 0.100 (T.P.) +0.004 0.020 -0.005 0.043 MIN. 0.1380.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.300 (T.P.) 0.256 0.010 +0.004 -0.003 0.01 0.043 MIN. 015 P16C-100-300B-1 67 PD6708 16 PIN PLASTIC SOP (300 mil) 16 9 detail of lead end 1 A G 8 H I J F K E C D M N M B L NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 10.46 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3 P INCHES 0.412 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3 P16GM-50-300B-4 68 PD6708 11. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (IEI-1207). For soldering methods and conditions other than those recommended, please contact NEC representative. Table 11-1. Surface Mount Type Soldering Conditions PD6708GS : 16-pin plastic SOP (300 mil) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 230 C, Reflow time: 30 seconds or less (at 210 C or higher), Number of reflow processes: 1 Package peak temperature: 215 C, Reflow time: 40 seconds or less (at 200 C or higher), Number of reflow processes: 1 Pin temperature: 300 C or below, Flow time: 3 seconds or less (per side of device) Symbol IR30-00-1 VPS reflow VP15-00-1 Partial heating -- Caution Use of more than one soldering method should be avoided (except for partial heating). Table 11-2. Hole-Through Type Soldering Conditions PD6708CX : 16-pin plastic DIP (300mil) Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Solder temperature: 260 C or below, Flow time: 10 seconds or less Pin temperature: 300 C or below, Flow time: 3 seconds or less (per pin) 5 Caution Wave soldering is used on the pin only, and care must be taken to prevent solder from coming into direct contact with the package body. 69 PD6708 5 APPENDIX MAJOR DIFFERENCES BETWEEN PD6708 AND PD72042A, PD72042B Part Number Parameter Oscillation frequency (fX) Supply voltage (VDD) Operating ambient temperature (TA) IEBus Communication mode Driver/receiver External protection resistor Transmit buffer Receive buffer Interfacing with microcontroller Note PD6708 PD72042A PD72042B 12 MHz 5 V 10 % -40 to +85 C Modes 0, 1, and 2 Provided Not necessary 4 Bytes 20 Bytes Serial interface (3-wire) MSB first 6 MHz Necessary (connect 180 in series to BOS+ and BOS-) 33 Bytes 40 Bytes Serial interface (3-wire/2-wire) MSB first 16-pin SOP (375 mil) LSB first Package 16-pin SOP (300 mil) 16-pin DIP (300 mil) Note Setting commands/data and related pins differs between the PD6708 and PD72042A, PD72042B. 70 PD6708 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 71 PD6708 IEBus and Inter Equipment Bus are trademarks of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 |
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